1. Field of the Invention
The present invention relates to a thin film transistor array substrate, and more particularly, to a method of fabricating a thin film transistor array substrate having a patterning process.
2. Description of the Related Art
In general, liquid crystal display (LCD) devices control light transmittance of liquid crystal material using an electric field, thereby displaying a picture. The liquid crystal display device, in which a common electrode formed on an upper substrate and a pixel electrode formed on a lower substrate are arranged facing each other, drives a liquid crystal according to an electric field formed between the common electrode and the pixel electrode.
The liquid crystal display device comprises a thin film transistor array substrate (or a lower substrate) and a color filter array substrate (or an upper substrate) facing and joining each other, a spacer for uniformly maintaining a cell gap between two substrates, and liquid crystal injected into the cell gap maintained by the spacer. The thin film transistor array substrate includes a plurality of signal lines, a plurality of thin film transistors, and an alignment film for liquid crystal alignment thereon. The color filter array substrate includes a color filter for representing a color, a black matrix for preventing light leakage, and an alignment film for liquid crystal alignment thereon.
FIG. 1 is a plan view illustrating a related art thin film transistor array substrate, and FIG. 2 is a sectional view of the thin film transistor array substrate taken along line II–II′ in FIG. 1.
Referring to FIGS. 1 and 2, the related art thin film transistor array substrate includes a gate line 2, a data line 4, and a gate insulating film 12 therebetween formed on a lower substrate 1 with the gate line 2 and the data line 4 intersecting each other. A thin film transistor 30 is formed at each intersection, and a pixel electrode 22 is formed in a pixel region 5 defined by the intersection. A storage capacitor 40 is formed at an overlap portion between the gate line 2 and a storage electrode 28. A gate pad 50 is connected to the gate line 2, and a data pad 60 connected to the data line 4. The gate line 2 supplying a gate signal and the data line 4 supplying a data signal are formed in an intersection structure, thereby defining the pixel region 5. The thin film transistor 30 responds to the gate signal of the gate line 2 so that the pixel signal of the data line 4 is charged to the pixel electrode 22.
To this end, the thin film transistor 30 includes a gate electrode 6 connected to the gate line 2, a source electrode 8 connected to the data line 4 and a drain electrode 10 connected to the pixel electrode 22. Further, the thin film transistor 30 includes an active layer 14 overlapping the gate electrode 6 with the gate insulating film 12 positioned between the active layer 14 and the gate electrode 6 to define a channel between the source electrode 8 and the drain electrode 10. The active layer 14 is formed overlapping the data line 4, a lower data pad electrode 62 and the storage electrode 28. On the active layer 14, an ohmic contact layer 16 for making an ohmic contact with the data line 4, the source electrode 8, the drain electrode 10, the lower data pad electrode 62 and the storage electrode 28 is further formed. The pixel electrode 22, which is connected to the drain electrode 10 of the thin film transistor 30 via a first contact hole 20 passing through a passivation film 18, is formed in the pixel region 5.
Accordingly, an electric field is formed between the pixel electrode 22 to which the pixel signal is supplied via the thin film transistor 30 and a common electrode to which the reference voltage is supplied. Moreover, the liquid crystal molecules arranged between the thin film transistor array substrate and the color filter array substrate by the electric field rotate due to a dielectric anisotropy. The light transmittance of the pixel region 5 differs in accordance with a rotation amount of the liquid crystal molecules, thereby enabling representation of pictures.
The storage capacitor 40 includes a gate line 2, a storage electrode 28 overlapping the gate line 2 with the gate insulating film 12, the active layer 14 and the ohmic contact layer 16 positioned therebetween, and a pixel electrode 22 connected to the storage electrode 28 via a second contact hole 42 formed in the passivation film 18. The storage capacitor 40 allows a pixel signal charged in the pixel electrode 22 to be stably maintained until the next pixel signal is charged.
The gate pad 50 is connected to a gate driver (not shown) and supplies a gate signal to the gate line 2. The gate pad 50 includes a lower gate pad electrode 52 extending from the gate line 2, and an upper gate pad electrode 54 connected to the lower gate pad electrode 52 using a third contact hole 56 passing through the gate insulating film 12 and the passivation film 18.
The data pad 60 is connected to a data driver (not shown) and supplies a data signal to the data line 4. The data pad 60 includes a lower data pad electrode 62 extending from the data line 4, and an upper data pad electrode 64 connected to the lower data pad electrode 62 using a fourth contact hole 66 passing through the passivation film 18.
A method of fabricating the thin film transistor substrate having the above-mentioned structure using a four mask process will be described in detail with reference to FIGS. 3A to 3H.
First, as shown in FIG. 3A, a gate metal layer 5 is formed on the upper substrate 1 by a deposition technique, such as a sputtering. A photo-resist pattern 72 is then formed by a photolithography process, such as an exposure process, using a first mask 70 defining a shielding region S2 and an exposure region S1, and a developing process. The gate metal layer 5 is patterned by an etching process using the photo-resist pattern 72, thereby forming a first conductive pattern group including the gate line 2, the gate electrode 6, and the lower gate pad electrode 52 on the lower substrate 1, as shown in FIG. 3B.
The gate insulating film 12, an amorphous silicon layer 15, an n+amorphous silicon layer 17, and a data metal layer 19 are sequentially formed on the lower substrate 1 provided with the first conductive pattern group by deposition techniques, such as the plasma enhanced chemical vapor deposition (PECVD) and the sputtering, etc, as shown in FIG. 3C.
Then, a photo-resist pattern 76 is formed by a photolithography process including an exposure process using a second mask 74 defining an exposure region S1, a shielding region S2 and a partial exposure region S3, and a developing process. In this case, a diffractive exposure mask having a diffractive exposing portion at a channel portion of the thin film transistor is used as a second mask 74, thereby allowing the photo-resist pattern 76 of the channel portion to have a lower height than photo-resist patterns of other regions. Subsequently, a data metal layer 19 is then patterned by a wet etching process using the photo-resist pattern 76, thereby forming a second conductive pattern group including the data line 4, the source electrode 8, the drain electrode 10 being integral to the source electrode 8 and the storage electrode 28, as shown in FIG. 3D. Next, the amorphous silicon layer and the n+ amorphous silicon layer are patterned at the same time by a dry etching process using the same photo-resist pattern, thereby forming the ohmic contact layer 16 and the active layer 14. The photo-resist pattern having a relatively low height is removed from the channel portion by ashing, and thereafter, the data metal layer and the ohmic contact layer 16 of the channel portion are etched by the dry etching process. Thus, the active layer 16 of the channel portion is exposed so that the source electrode 8 is separated from the drain electrode 10.
The passivation film 18 is entirely formed on the gate insulating film 12 provided with the second conductive pattern group by a deposition technique, such as plasma enhanced chemical vapor deposition (PECVD), as shown in FIG. 3E. Then, a photo-resist pattern 80 is formed by a photolithography process including an exposure process using a third mask 78 defining a shielding region S2 and an exposure region S1, and a developing process, on the passivation film 18. The passivation film 18 is patterned by etching using the photo-resist pattern 80, thereby forming first to fourth contact holes 20, 42, 56 and 66, as shown in FIG. 3F.
As shown in FIG. 3G, a transparent conductive film 23 is coated onto the passivation film 18 having the first to the fourth contact holes 20, 42, 56 and 66 by a deposition technique, such as the sputtering, etc. Then, a photo-resist pattern 84 is formed by a photolithography process including an exposure process using a fourth mask 82 defining a shielding region S2 and an exposure region S1, and a developing process. The transparent conductive film 23 is patterned by etching using the photo-resist pattern, thereby forming a third conductive pattern group including the pixel electrode 22, the upper gate pad electrode 54 and the upper data pad electrode 64.
As described above, in the thin film transistor array substrate and the method of fabricating the same, the photolithograph process includes a series of photo processes such as a coating process of a photo-resist, a mask arranging process, an exposing process, a developing process, and a stripping process. Here, the photolithography process requires a long processing time, a waste of a stripping solution for removing a photo-resist pattern and a photo-resist, and expensive equipment such as an exposure equipment. As a result, as substrate size becomes large and pattern size becomes small, exposing equipment becomes increasingly expensive accordingly.